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max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems ________________________________________________________________ maxim integrated products 1 19-0245; rev 0; 3/94 call toll free 1-800-998-8800 for free samples or literature. 1.0 scope 1.1 this specification covers the detail requirements for two data-acquisition systems. these circuits are processed in accordance with mil-std-883 and are fully compliant to paragraph 1.2.1. it is highly recommended that this data sheet be used as a baseline for new military or aerospace source control drawings. for typical applications and operating characteristics, consult maxim's standard data books. 1.2 part numbers device part number -1 max180am(x)l -2 max180bm(x)l -3 max180cm(x)l -4 MAX181am(x)l -5 MAX181bm(x)l -6 MAX181cm(x)l 1.3 package (x) package description j j-40 40-pin ceramic dual-in-line package (cerdip) d d-40 40-pin ceramic sidebraze package note: see package information section for drawing and dimensions. 1.4 absolute maximum ratings v dd to dgnd .....................................................................................................................-0.3v, +7v v ss to dgnd ....................................................................................................................-0.3v, -17v agnd to dgnd....................................................................................................-0.3v, (v dd + 0.3v) ain_, muxout, adcin, refadj, offadj to refin.................................................................................................-0.3v, (v dd + 0.3v) refin to dgnd ....................................................................................................+0.3v, (v ss - 0.3v) c s , w r , r d , clk, a2-a0, bip, diff, hben to dgnd ...................................................................................-0.3v, (v dd + 0.3v) b u s y , d0-d11 to dgnd ......................................................................................-0.3v, (v dd + 0.3v) continuous power dissipation (t j = +150?) to +70?.........................................................................................................................1000mw derates above +70? by ..............................................................................................10mw/? operating temperature range................................................................................-55? to +125? storage temperature range ...................................................................................-65? to +160? lead temperature (soldering, 10sec) ...................................................................................+300?
max180/MAX181/883b 1.5 thermal resistance q jc = 25?/w for j-40 q ja = 50?/w for j-40 2.0 requirements 2.1 electrical performance characteristics are specified in table 1 and apply over the full ambient operating temperature range, unless otherwise specified. table 1. electrical performance characteristics complete, 8-channel, 12-bit data-acquisition systems 2 _______________________________________________________________________________________ symbol group a sub- groups limits min max units resolution n all 1, 2, 3 12 max18_a -1, -4 ?/4 integral nonlinearity error inl max18_b/c -2, -3, -5, -6 ? lsb dnl guaranteed montonic over temp. all 1, 2, 3 ? all 1, 2, 3 ? all 1, 2, 3 ? all 1, 2, 3 ?0 gain-error tempco (notes 5, 6) all ? ppm/? differential nonlinearity all 1, 2, 3 ?5 lsb bipolar gain error unipolar gain error bipolar offset error (note 4) unipolar offset error (note 4) signal-to-noise + distortion ratio sinad 10khz input signal, 100khz sampling rate, bipolar mode, t a = +25? all 9 70 db total harmonic distortion (up to the 5th harmonic) thd 10khz input signal, 100khz sampling rate, bipolar mode, t a = +25? all 9 -80 db spurious-free dynamic range sfdr 10khz input signal, 100khz sampling rate, bipolar mode, t a = +25? all db full-power sampling bandwidth (note 5) in track mode, undersampled all 9 80 mhz track/hold acquisition time (note 5) t acq all 1.875 ? asynchronous hold mode (note 5) conversion time t conv rom, slow-memory, and i/o port modes; 15-16 clock cycles all 9, 10, 11 9.375 10.000 ? 6 conditions (notes 1, 2) characteristics device types bits 7.500 8.125 1, 2, 3 lsb lsb lsb lsb accuracy (note 3) dynamic performance (note 3)
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems _______________________________________________________________________________________ 3 voltage range ain_, muxout, and adcin all 1, 2, 3 refin v dd ain_ to agnd all 1, 2, 3 0 5.0 unipolar, differential range ain_+ to ain_- all 1, 2, 3 0 5.0 bipolar, single-ended range ain_ to agnd all 1, 2, 3 -2.5 2.5 bipolar, differential range ain_+ to ain_- all 1, 2, 3 -2.5 2.5 v ain_, max180 -1, -2, -3 ?.0 input current adcin, MAX181 -4, -5, -6 1, 2, 3 ?.1 ? mux-on resistance r on ain_ = 2.5v, i muxout = 1.25ma, MAX181 -4, -5, -6 1, 2, 3 2 table 1. electrical performance characteristics (continued) mux-on leakage current i on ain_ = muxout = ?v, MAX181 -4, -5, -6 1, 2, 3 ?00 k i in(off) ain_ = ?v, v out = ?v, MAX181 -4, -5, -6 1, 2, 3 ?00 mux-off leakage current i out(off ) ain_ = ?v, v out = ?v, MAX181 -4, -5, -6 1, 2, 3 ?00 na ain_, adcin -4, -5, -6 35 input capacitance (note 5) c in muxout -4, -5, -6 45 pf input range (note 5) all -4.92 -5.08 v input current all 1, 2, 3 -2 ma input resistance all 1, 2, 3 2.5 k vref output voltage t a = +25? all 1 -4.98 -5.02 v max18_a/b -1, -2, -4, -5 25 vref output tempco (note 7) max18_c -3, -6 1, 2, 3 45 ppm? vref load regulation (note 8) i out = 0ma to 5ma, t a = +25? -3, -6 1 1.0 mv/ma input current v refadj , v offadj = v dd to refin all 1, 2, 3 ? ? disable threshold all 1, 2, 3 4.5 v refadj adjustment range refin max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems 4 _______________________________________________________________________________________ characteristics conditions device types group a sub- groups limits min max units mode all 1, 2, 3 0.5 input low voltage v il c s , r d , w r , clk, a2-a0, diff, bip, hben all 1, 2, 3 0.8 v mode all 1, 2, 3 4.5 input high voltage v ih c s , r d , w r , clk, a2-a0, diff, bip, hben all 1, 2, 3 2.4 v input mid-level voltage v mid mode all 1, 2, 3 1.5 3.5 v table 1. electrical performance characteristics (continued) t a = +25? 1 ?00 mode t a = t min to t max 1, 2, 3 ?00 t a = +25? 1 ? i in c s , r d , w r , clk, a2-a0, diff, bip, hben t a = t min to t max 1, 2, 3 ?0 ? input current c in 15 pf output low voltage v ol d11-d0, b u s y , rdy, isink = 1.6ma all 1, 2, 3 0.4 v output high voltage v oh d11-d0, b u s y , rdy, isource = 360? all 1, 2, 3 4.0 v floating-state output capacitance (note 5) c out all 15 pf v dd 4.75 5.25 supply voltage (note 2) v ss 1, 2, 3 -11.40 -15.75 v i dd v dd = 5v all 1, 2, 3 7.0 supply current i ss v ss = -15v 10.0 ma power dissipation pd v dd = 5v, v ss = -15v 1, 2, 3 155 mw input near fs, v ss = -12v, v dd = 4.75v to 5.25v ? input near fs, v dd = 5v, v ss = -14.25v to -15.75v ?/2 power-supply rejection with internal reference psr input near fs, v dd = 5v, v ss = -11.4v to -12.6v all 1, 2, 3 ?/2 lsb input capacitance (note 5) symbol input floating voltage (note 5) v flt mode all 2.5 v floating-state leakage current i lkg d11-d0, v out = 0v to v dd all 1, 2, 3 ?0 ? all all all all logic inputs logic outputs power requirements
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems _______________________________________________________________________________________ 5 c s to r d setup time t 1 (note 5) all 0 ns c s to r d hold time t 2 all 9, 10, 11 0 ns c s to w r setup time t 3 all 9, 10, 11 0 ns c s to w r hold time t 4 (note 5) all 0 ns w r low pulse width t 5 all 9, 10, 11 120 ns w r high pulse width t 6 mode = 0 or 1 (note 5) all 200 ns all 9 80 data in to w r setup time t 7 10, 11 120 ns data in to w r hold time t 8 all 9, 10, 11 0 ns 9 160 ns w r rising to b u s y delay t 9 c l = 50pf, mode = 1 all 10, 11 200 all 9 220 ns w r falling to b u s y delay t 10 c l = 50pf, mode = open 10, 11 280 9 100 ns r d low pulse width t 11 all 10, 11 150 r d high pulse width t 12 (note 5) all 200 ns 9 80 ns data in to r d setup time t 13 all 10, 11 120 data in to r d hold time t 14 all 9, 10, 11 0 ns 9 150 ns r d to b u s y fall delay t 15 c l = 50pf all 10, 11 200 9 100 ns r d to data out valid t 16 c l = 100pf (note 10) all 10, 11 150 all 9 50 ns r d to data out three- state (notes 10, 11) 10, 11 75 all 9 80 ns hben to r d or w r setup time t 18 10, 11 120 characteristics symbol conditions (notes 3, 9) device types group a sub- groups limits min max units t 17 table 2. timing characteristics
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems 6 _______________________________________________________________________________________ characteristics symbol conditions (notes 3, 9) device types group a sub- groups limits min max units all 9 110 ns c s to r e a d y fall delay t 20 10, 11 150 all 9 125 ns b u s y to data out valid t 21 c l = 100pf (note 10) 10, 11 170 c s , r d or w r to clk setup time for 15 clock conversion t 22 (note 5) all 220 ns c s , r d or w r to clk setup time for 16 clock conversion t 23 (note 5) all 0 ns hben to r d or w r hold time t 19 all 9, 10, 11 0 ns c l = 50pf table 2. timing characteristics (continued) note 1: v dd = +5v ?%, v ss = -12v ?% or -15v ?%, refin = -5v, internal reference mode, bipolar mode, slow-memory mode (see text), f clk = 1.6mhz external, max180/MAX181 all grades, t a = t min to t max , unless otherwise noted. note 2: performance at power-supply tolerance limits guaranteed by power-supply rejection test. note 3: v dd = +5v, v ss = -12v, f clk = 1.6mhz, internal reference mode, t a = t min to t max , unless otherwise noted. note 4: typical change over temperature is ?lsb. note 5: characteristics supplied for use as a typical design limit, but not production tested. note 6: fs tempco = ? fs/ ? t, where fs is full-scale change from t a = +25? to t min or to t max . note 7: refin tc = ? refin/ ? t, where ? refin is reference voltage change from t a = +25? to t min or to t max . note 8: load current should remain constant during conversion. this current is in addition to the dac input current. note 9: all inputs are 0v to +5v swing with t r = t f = 5ns (10% to 90% of 5v) and timed from a +1.6v voltage level. note 10: t 16 and t 21 are measured with the load circuits of figure 1 (c l = 100pf) and defined as the time required for an output to cross 0.8v or 2.4v. note 11: t 17 is defined as the time required for the data lines to change 0.5v when the circuit load is as shown in figure 2 (c l = 10pf). dgnd 3k c l dn +5v 3k c l b. v ol to high-z a. v oh to high-z dn dgnd figure 1. load circuits for bus-relinquish time
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems _______________________________________________________________________________________ 7 3.0 quality assurance 3.1 sampling and inspection procedures shall be in accordance with mil-m-38510 and, to the extent specified, with mil-std-883. 3.2 screening shall be in accordance with method 5004 of mil-std-883. burn-in test (method 1015): (1) test condition a, b, c, or d. (2) t a = +125?, minimum. (3) interim and final electrical test requirements shall be as specified in table 3. 3.3 quality conformance inspection shall be in accordance with method 5005 of mil-std-883 includ- ing groups a, b, c and d inspection. group a inspection: (1) tests as specified in table 3. (2) selected subgroups in tables 1 and 2, method 5005 of mil-std-883 shall be omitted. (3) subgroup 4 (c in and c out ) shall be measured only for the initial test and after process or design changes, which may affect input or output capacitance. 3.4 groups c and d inspections: a. end-point electrical parameters shall be specified in tables 1 and 2. b. steady-state life test (method 1005 of mil-std-883): (1) test conditions a, b, c, or d. (2) t a = +125?, minimum. (3) test duration, 1000 hours, except as permitted by method 1005 of mil-std-883. table 3. electrical test requirements mil-std-883 test requirements subgroups (per method 5005, tables 1 and 2) interim electrical parameters (method 5004) 1 final electrical parameters (method 5004) 1,*2, 3, 9 group a test requirements (method 5005) 1, 2, 3 ,4,** 9 groups c and d end-point electrical parameters (method 5005) 1 additional electrical subgroups for group c periodic inspections 1 *pda applies to subgroup 1 only. **subgroup 4 shall be tested at initial qualification and upon redesign. sample size will be 5 units.
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems 8 _______________________________________________________________________________________ 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 v dd a2 a1 ad ain3 ain2 ain1 ain0 uni/bip se/diff busy cs ain7 ain6 ain5 ain4 wr rd agnd refin 30 29 28 27 26 25 24 23 22 21 hben clkin d0 d1 d2 d3 d4 d5 d6 d7 11 12 13 14 15 16 17 18 19 20 mode vref refadj refout d9 d10 d11 v ss dgnd d8 gnd 30 w +5v -15v 30 w gnd c1 note 1: c1 = 4.7 m f ceramic or tantalum ?0% max180 + latch and three-state output -5v buried zener mux t/h comp control logic dac sar ain0 ain1 ain2 ain3 ain4 ain5 ain6* ain7* refout refadj ** * muxout** adcin** offadj v dd agnd dgnd v ss d11 d0 busy * max180 only control refin + - **MAX181 only 4.1 life test/burn-in circuits 4.2 functional diagram 4.0 detailed description
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems _______________________________________________________________________________________ 9 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 v dd a2 a1 ad ain3 ain2 ain1 ain0 top view max180 bip diff busy cs (adcin)**ain7* (muxout)**ain6* ain5 ain4 wr rd agnd refin 30 29 28 27 26 25 24 23 22 21 hben clkin d0 d1 d2 d3 d4 d5 d6 d7 11 12 13 14 15 16 17 18 19 20 mode offadj refadj refout d9 d10 d11 v ss dgnd d8 *max180 only **max 181 only MAX181 4.3 pin configuration 4.4 pin description positive supply: +5v input (substrate connected to v dd ) 40 40 v dd multiplexer channel address input: a2 = msb, a0 = lsb 37-39 37-39 a0-a2 unipolar mode: bip = 0, bipolar mode: bip = 1 36 36 bip single-ended mode: diff = 0, differential mode: diff = 1 35 35 diff b u s y output 34 34 b u s y c h i p - s e l e c t input 33 33 c s w r i t e input (mode = 1 or open) r e a d y output (mode = 0) 32 32 w r r e a d input 31 31 r d high-byte enable input 30 30 hben clock input, ttl/cmos compatible 29 29 clkin three-state data outputs, lsb = d0 21-28 21-28 d7-d0 digital ground 20 20 dgnd three-state data outputs, msb = d11 16-19 16-19 d11-d8 negative supply: -15v or -12v 15 15 v ss interface mode select pin. 14 14 mode offset adjust. connect to v dd if not required. 13 13 offadj -5v reference adjust. connect to v dd if not required. 12 12 refadj -5v reference output 11 11 refout analog ground 10 10 agnd reference input 9 9 refin analog input to track/hold 8 adcin multiplexer output 7 muxout analog inputs to the mux: 0v to +5v unipolar, -2.5v to +2.5v bipolar 7, 8 ain6-ain7 analog inputs to the mux: 0v to +5v unipolar, -2.5v to +2.5v bipolar 1-6 1-6 ain0-ain5 function MAX181 max180 name
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems 10 ______________________________________________________________________________________ max180 MAX181 mux t/h mux t/h ain0 ain7 agnd diff = 1 diff = 0 ain0 ain5 agnd muxout adcin diff = 1 diff = 0 control inputs status output to m p data bus busy cs wr rd hben a0 a1 a2 bip diff d0/8 d1/9 d2/10 d3/11 d4 d5 d6 d7 d8 d9 d10 d11 write x x x x x x x diff bip a2 a1 a0 read d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 max180 MAX181 figure 2. multiplexer channel configuration figure 3. input/output port mode (12-bit-wide data bus shown) 4.5 address vs. channel selection table MAX181 a2 a1 se/diff ain1 ain2 ain3 com 1 0 0 0 1 0 0 0 + 1 0 1 0 + 0 0 1 0 + 1 0 0 1 0 0 1 1 0 1 1 0 +, 1 1 0 part(s) max180/MAX181 max180/MAX181 max180/MAX181 max180/MAX181 max180/MAX181 max180/MAX181 max180 MAX181 max180 a0 0 1 0 1 0 1 0 0 1 ain0 + ain7 + ain6 + muxout connected to agnd ain5 + ain4 + ch 0-5, and muxout are open max180/MAX181 0 0 0 1 + max180/MAX181 0 0 1 1 + max180/MAX181 0 1 0 1 + max180/MAX181 0 1 1 1 + max180/MAX181 1 0 0 1 + max180/MAX181 1 0 1 1 + max180 1 1 0 1 + max180 1 1 1 1 + MAX181 1 1 0 1 muxout connected to agnd +, MAX181 1 1 1 1 ch 0-5, and muxout are open
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems ______________________________________________________________________________________ 11 hben wr rd busy data in cs data out hold track 3 clk t 8 t 7 data valid t 9 t 5 t 3 t 4 t 1 t 11 t 2 t 12 t 17 t 16 new data d7-d0 t 16 new data t 17 d11-d8 t 1 t 11 t 2 t 3 t 18 t 19 t 5 t 4 t 9 t 7 data valid t 8 3 clk t conv figure 4b. input/output port-mode timing, two-byte read (mode = 1) 4.6 timing diagrams cs wr rd busy data in data out hold track t 5 t 3 t 4 t 9 t conv t 7 t 8 data valid 3 clk t 16 t 17 t 11 t 1 t 2 t 3 t 5 t 4 t 9 t 7 t 8 data valid new data d11-d0 3 clk figure 4a. input/output port-mode timing, parallel read (mode = 1, hben = 0)
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems 12 ______________________________________________________________________________________ hben cs rd busy data in data out wr (ready output) hold track t 18 t 1 t 15 t 14 data valid t 16 old data new data t 20 3 clk d7-d0 d7-d0 t 21 t 17 t 14 t 17 t 16 new data d11-d8 t 20 t 14 t 13 t 15 t 1 t 2 t 1 t 2 t 19 t 19 t 18 data valid data valid t 13 t conv t 18 t 13 figure 5b. slow-memory mode timing, two-byte read (mode = 0) cs rd busy data in data out wr (ready output) hold track t 1 t 15 t 13 data valid t 16 t 20 old data d11-d0 3 clk t 21 t 17 new data d11-d0 3 clk t 14 t 16 t 15 t 1 t 2 data valid t conv t 14 t 20 t 13 figure 5a. slow-memory mode timing, parallel read (mode = 0, hben = 0)
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems ______________________________________________________________________________________ 13 cs rd busy data in data out wr (ready output) hold track t 1 t 2 t 15 t 14 t 16 data valid old data d11-d0 t 17 t 20 3 clk t 20 3 clk t 16 new data d11-d0 t 14 t 1 t 15 t 17 t 13 data valid t conv t 11 t 2 t conv t 11 t 13 figure 6a. rom mode timing, parallel read (mode = 0, hben = 0) data valid data valid data valid old data new data new data hben cs rd busy data in data out wr (ready output) hold track t 18 t 19 t 1 t 2 t 1 t 15 t 14 t 13 t 14 t 16 t 17 t 16 t 20 3 clk d7-d0 t 17 d11-d8 3clk t 16 t 17 t 13 t 15 t 2 t 1 t 2 t 19 t 18 t 19 t 13 t conv t 11 t 18 t 11 t 12 d7-d0 t 14 t 11 figure 6b. rom mode timing, two-byte read (mode = 0)
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems 14 ______________________________________________________________________________________ hben cs wr rd busy data in data out hold track t 3 t 5 t 4 t 18 t 18 t 19 t 3 t 4 t 5 t 10 t 7 t 8 t 7 t 8 t 16 t 17 d7-do t 16 t 17 d11-d8 new data new data t 1 t 2 t 1 t 2 t 18 t 19 data valid data valid t conv t 19 t 11 t 12 t 11 t 6 figure 7b. asynchronous hold mode timing, two-byte read (mode = open circuit) t 5 t 3 t 4 t 3 t 4 t 5 t 18 t 19 t 10 t 7 t 8 t 7 t 8 t 1 t 11 t 16 t 17 new data data valid data valid t 2 hben cs wr rd busy data in data out hold track t 6 t conv d11-d0 figure 7a. asynchronous hold mode timing, parallel read (mode = 0pen circuit)
max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems ______________________________________________________________________________________ 15 t 22 t 23 clk t 22 > 220ns conversion takes 15 clocks t 23 > 0ns conversion takes 16 clocks * a wr rising edge starts a conversion in input/output port mode (figures 4a, 4b) cs, rd, or wr * figure 8. c s ,r d , or w r to clk setup and hold time for synchronous operation
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1994 maxim integrated products printed usa is a registered trademark of maxim integrated products. max180/MAX181/883b complete, 8-channel, 12-bit data-acquisition systems 4.7 package information c l d e e a a b2 b dim a b b2 c d e e e a l q s1 min ? 0.014 0.045 0.008 ? 0.510 0.125 0.015 0.005 max 0.225 0.026 0.065 0.018 2.096 0.620 0.200 0.070 min ? 0.36 1.14 0.20 ? 12.95 3.18 0.38 0.13 max 5.72 0.66 1.65 0.46 53.24 15.75 5.08 1.78 inches millimeters 2.54 bsc 15.24 bsc 0.100 bsc 0.600 bsc e 21-0018b 40-pin sidebraze dual-in-line package q s1

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